In the formation of semiconductor chip circuitry such as sources and drains of field effect transistors, it is important that the active areas of the transistors be separated so that electrical current does not flow between them in an unintended manner. Active areas of a transistor are defined as the areas of a transistor where current flows, such as the source and drain of an insulated gate field effect transistor. It is desirable to place unassociated transistors as close together as possible to minimize the total chip area taken up by the transistors. As the space between unassociated transistors shrinks, there is still a need to maintain total electrical isolation between the unassociated transistors. Prior solutions have relied on thick field oxides to achieve isolation, as seen in prior art FIG. 1.
One problem with the use of field oxide isolation to provide isolation of active areas of adjacent unassociated transistors arises during formation of the oxide layer. When the oxide is formed, it has the tendency to creep under a masking nitride layer, toward the gates of the unassociated transistors. Any misalignment of the gates with respect to the oxide layer causes unbalancing of the transistors, especially when trying to obtain close spacing to conserve real estate on the chip. This unbalancing is the result of one active area being larger than the other active area, and exhibiting different resistance and capacitance. To minimize such problems, the distance between the transistors is increased, resulting in less efficient use of the chip. In dynamic random access memory chips, both efficient use of chip space, and precisely balanced circuits, such as are used in sense amplifiers are critical as the memory capacity of such chips increases.
There is a need to provide effective isolation of unassociated circuitry using as little chip real estate as possible while at the same time providing precisely balanced circuitry.